As the dimensions within integrated circuits have grown ever smaller, solutions have had to be found to problems relating to misalignment of succesive mask patterns relative to one another during processing. Thus, source and drain regions might not line up correctly relative to the gate, deposited contacts might not line up perfectly inside contact holes, and connections that were physically close together but had to be electrically isolated from one another might develop short circuits between them.
To overcome these problems, a variety of ingenious techniques have been introduced into the integrated circuit art. For example, alignment of source and drain relative to the gate was achieved by using the gate as a mask during ion implantation. The SALICIDE (self-aligned silicide) process took advantage of the fact that certain metals such as titanium or cobalt react when heated in contact with silicon to form conductive silicides but do not react with silicon oxide. Thus, oxide spacers on the vertical walls of the gate pedestal could be used to provide the necessary small, but well controlled, separation between the source and drain contacts and the gate contact.
Although the SALICIDE method made possible significant reductions in device size, as devices shrank even further shorting between the gate and the source/drain began to be a problem and an alternative approach had to be developed. This is the so-called SAC (self-aligned contact) method in which an anisotropic etch is used to form a contact hole that passes through the inter-poly oxide down to the source/drain surface. Perfect alignment of this contact hole relative to the source/drain is not needed since the spacers prevent uncovering of the vertical walls of the gate pedestal. Since etch-through of the spacers at their top (where they are very thin) cannot be avoided, the polysilicon gate pedestal is covered by a layer of silicon nitride (known as a hard mask) and the spacers formed so as to extend from the top of the hard mask to the bottom of the gate pedestal. During contact hole formation a certain amount of the hard mask material does get removed but sufficient remains so that when conductive material is deposited in the contact hole it does not short to the gate pedestal.
It has been the general practice to use the SALICIDE method for logic circuits because it made possible higher circuit performance and the SAC method for memory circuits because it allowed the cell size of the memory unit to be reduced. As long as logic and memory were on separate chips each process could be used without concern for its effect on the other. As part of the next major development in integrated circuits it has become necessary to place logic and memory circuits on the same chip. This avoids the delay introduced by off-chip drivers each time logic and memory communicate with one another. Thus, a process that allows the integration, at reasonable cost, of both the SAC and SALICIDE methods on a single chip is clearly needed. This is the subject matter of the present invention.
While there are many references in the prior art to both processes, none of these, to our knowledge, addresses the specific problem of integrating these different contacting methods for use on a single chip in both memory and logic circuits. Among the references that we found to be of interest we include Fang et al. (U.S. Pat. No. 5,668,035 September 1997) who teach formation of a memory chip with embedded logic but the problem of making optimum (and therefore different) contacts to the two areas is not addressed. Bashir et al. (U.S. Pat. No. 5,397,722 March 1995) teach a method for self-alignment in which silicon nitride spacers are formed on the contacting poly layer. The remaining poly is then oxidized following which the silicon nitride is removed and the now unprotected underlying poly is etched away. Yoo (U.S. Pat. No. 5,573,980 November 1996) shows how contact resistance may be reduced by depositing a thin layer of polysilicon prior to silicidation.
Lin (U.S. Pat. No. 5,668,065 September 1997) describe a process for simultaneously forming a self aligned contact, a local interconnect, and a self-aligned silicide in a semiconductor device. No distinction is drawn between logic and memory areas, so that selective removal of the hard mask (a key feature of the present invention) does not take place. Matthews (U.S. Pat. No. 5,134,083 July 1992) teaches the use of self-aligned interconnects in BICMOS circuits.